This invention relates to a level converting circuit for converting input signals into different level output signals, which is particularly suitable for a driving liquid crystal display element.
The level converting circuit is a circuit used for converting input signals into different level output signals, and is used when driving, for example, an active matrix type liquid crystal display element, in which case a power source of 12 to 15 V higher than 5 V of the usual digital circuit is employed and hence it becomes necessary to convert the voltage of 5 V into the higher voltage of 12 to 15 V.
In the prior art, a variety of level converting circuits have been proposed. In JP Utility Model KOKAI Publication No. 8230/1990, there is disclosed a level converting circuit making use of a current mirror circuit. On the other hand, FIG. 6 herein shows a typical conventional level converting circuit. The circuit shown in FIG. 6 is now briefly explained. An output signal VCK of an inverter 61 is supplied to the gate of an nMOS transistor 63, while an output signal VCKX is supplied to the gate of an nMOS transistor 64. The drains of the nMOS transistors 63 and 64 are connected to the drains of pMOS transistors 65 and 66 connected in a current mirror configuration. The drain of the nMOS transistor 64 is connected to the gate of an inverter made up of a pMOS transistor 68 and an nMOS transistor 67. Since a power source voltage V.sub.DD is supplied to the inverter and the MOS transistors 63, 64, the output signal of the inverter is converted into a level of 0 to V.sub.DD. It will be seen from FIG. 7, which is a waveform diagram showing these signals VCK, VCKX, that these signals VCK and VCKX are oppositely phased clock signals.
In operation, when the signal VCK is a high level (H-level) signal and the signal VCKX is a low level (L-level) signal, the nMOS transistor 63 is turned on and the current flowing through the transistor 63 also flows through the pMOS transistor 66 by the current mirror effect. Since the nMOS transistor 64 is turned off, the drain of the nMOS transistor 64 is charged so that the output level of the inverter is at the ground level. If the signals are of reversed polarities, the nMOS transistor 64 is turned on and the nMOS transistor 63 is turned off. The result is that the inverter gate is discharged towards the ground level, while the output level of the inverter is increased towards the V.sub.DD level.
In the case of a circuit for driving a liquid crystal device, the nMOS transistors 63 and 64 are constituted by thin-film field effect transistors. Thus the threshold voltage Vth of the nMOS transistors 63 and 64 is of a larger value, resulting in larger process fluctuations. If for example the threshold voltage Vth is increased, the current flowing in the turn-on state is diminished and the charging/discharging rate at a node (inverter gate) is lowered. The result is that the waveform, which should be rectangular, becomes sinusoidal, as shown by a curve PA in FIG. 8, and exhibits blunted rising and falling flanks.
For overcoming such drawback, it may be contemplated to increase the size of the nMOS transistors 63 and 64 significantly. However, in such case, the chip area is increased, or the operating speed can not be increased due to the increased self-capacitance.